Mitigated FPGA design of multi-gigabit transceivers for application in high radiation environments of High Energy Physics experiments

Research output: Contribution to journal › Journal article › Research › peer-review

Standard

Mitigated FPGA design of multi-gigabit transceivers for application in high radiation environments of High Energy Physics experiments. / Brusati, M.; Camplani, A.; Cannon, M.; Chen, H.; Citterio, M.; Lazzaroni, M.; Takai, H.; Wirthlin, M.

In: Measurement: Journal of the International Measurement Confederation, Vol. 108, 2017, p. 171-192.

Research output: Contribution to journal › Journal article › Research › peer-review

Harvard

Brusati, M, Camplani, A, Cannon, M, Chen, H, Citterio, M, Lazzaroni, M, Takai, H & Wirthlin, M 2017, 'Mitigated FPGA design of multi-gigabit transceivers for application in high radiation environments of High Energy Physics experiments', Measurement: Journal of the International Measurement Confederation, vol. 108, pp. 171-192. https://doi.org/10.1016/j.measurement.2017.02.025

APA

Brusati, M., Camplani, A., Cannon, M., Chen, H., Citterio, M., Lazzaroni, M., Takai, H., & Wirthlin, M. (2017). Mitigated FPGA design of multi-gigabit transceivers for application in high radiation environments of High Energy Physics experiments. Measurement: Journal of the International Measurement Confederation, 108, 171-192. https://doi.org/10.1016/j.measurement.2017.02.025

Vancouver

Brusati M, Camplani A, Cannon M, Chen H, Citterio M, Lazzaroni M et al. Mitigated FPGA design of multi-gigabit transceivers for application in high radiation environments of High Energy Physics experiments. Measurement: Journal of the International Measurement Confederation. 2017;108:171-192. https://doi.org/10.1016/j.measurement.2017.02.025

Author

Brusati, M. ; Camplani, A. ; Cannon, M. ; Chen, H. ; Citterio, M. ; Lazzaroni, M. ; Takai, H. ; Wirthlin, M. / Mitigated FPGA design of multi-gigabit transceivers for application in high radiation environments of High Energy Physics experiments. In: Measurement: Journal of the International Measurement Confederation. 2017 ; Vol. 108. pp. 171-192.

Bibtex

@article{836739e76a8e4fceaa769368ccc3cf3e,
title = "Mitigated FPGA design of multi-gigabit transceivers for application in high radiation environments of High Energy Physics experiments",
abstract = "SRAM-based Field Programmable Gate Array (FPGA) logic devices are very attractive in applications where high data throughput is needed, such as the latest generation of High Energy Physics (HEP) experiments. FPGAs have been rarely used in such experiments because of their sensitivity to radiation. The present paper proposes a mitigation approach applied to commercial FPGA devices to meet the reliability requirements for the front-end electronics of the Liquid Argon (LAr) electromagnetic calorimeter of the ATLAS experiment, located at CERN. Particular attention will be devoted to define a proper mitigation scheme of the multi-gigabit transceivers embedded in the FPGA, which is a critical part of the LAr data acquisition chain. A demonstrator board is being developed to validate the proposed methodology. Mitigation techniques such as Triple Modular Redundancy (TMR) and scrubbing will be used to increase the robustness of the design and to maximize the fault tolerance from Single-Event Upsets (SEUs).",
keywords = "FPGA, High Energy Physics, Instrumentation, Measurement, Reliability, Scrubbing",
author = "M. Brusati and A. Camplani and M. Cannon and H. Chen and M. Citterio and M. Lazzaroni and H. Takai and M. Wirthlin",
note = "Publisher Copyright: {\textcopyright} 2017 Elsevier Ltd",
year = "2017",
doi = "10.1016/j.measurement.2017.02.025",
language = "English",
volume = "108",
pages = "171--192",
journal = "Measurement: Journal of the International Measurement Confederation",
issn = "0263-2241",
publisher = "Elsevier",

}

RIS

TY - JOUR

T1 - Mitigated FPGA design of multi-gigabit transceivers for application in high radiation environments of High Energy Physics experiments

AU - Brusati, M.

AU - Camplani, A.

AU - Cannon, M.

AU - Chen, H.

AU - Citterio, M.

AU - Lazzaroni, M.

AU - Takai, H.

AU - Wirthlin, M.

N1 - Publisher Copyright: © 2017 Elsevier Ltd

PY - 2017

Y1 - 2017

N2 - SRAM-based Field Programmable Gate Array (FPGA) logic devices are very attractive in applications where high data throughput is needed, such as the latest generation of High Energy Physics (HEP) experiments. FPGAs have been rarely used in such experiments because of their sensitivity to radiation. The present paper proposes a mitigation approach applied to commercial FPGA devices to meet the reliability requirements for the front-end electronics of the Liquid Argon (LAr) electromagnetic calorimeter of the ATLAS experiment, located at CERN. Particular attention will be devoted to define a proper mitigation scheme of the multi-gigabit transceivers embedded in the FPGA, which is a critical part of the LAr data acquisition chain. A demonstrator board is being developed to validate the proposed methodology. Mitigation techniques such as Triple Modular Redundancy (TMR) and scrubbing will be used to increase the robustness of the design and to maximize the fault tolerance from Single-Event Upsets (SEUs).

AB - SRAM-based Field Programmable Gate Array (FPGA) logic devices are very attractive in applications where high data throughput is needed, such as the latest generation of High Energy Physics (HEP) experiments. FPGAs have been rarely used in such experiments because of their sensitivity to radiation. The present paper proposes a mitigation approach applied to commercial FPGA devices to meet the reliability requirements for the front-end electronics of the Liquid Argon (LAr) electromagnetic calorimeter of the ATLAS experiment, located at CERN. Particular attention will be devoted to define a proper mitigation scheme of the multi-gigabit transceivers embedded in the FPGA, which is a critical part of the LAr data acquisition chain. A demonstrator board is being developed to validate the proposed methodology. Mitigation techniques such as Triple Modular Redundancy (TMR) and scrubbing will be used to increase the robustness of the design and to maximize the fault tolerance from Single-Event Upsets (SEUs).

KW - FPGA

KW - High Energy Physics

KW - Instrumentation

KW - Measurement

KW - Reliability

KW - Scrubbing

U2 - 10.1016/j.measurement.2017.02.025

DO - 10.1016/j.measurement.2017.02.025

M3 - Journal article

AN - SCOPUS:85014247808

VL - 108

SP - 171

EP - 192

JO - Measurement: Journal of the International Measurement Confederation

JF - Measurement: Journal of the International Measurement Confederation

SN - 0263-2241

ER -

ID: 309282204